Remove unnecessary cr4 handling in vmx_set_cr0.

1) on x86_32, PAE should never be enabled in guest cr4, since we only
support pure IA32 VMX guest.
2) on x86_32p or x86_64, PAE should always be enabled in guest cr4,
since even pure IA32 guest uses PAE paging mode actually.

Signed-off-by: Xin Li <xin.b.li@intel.com>
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>

diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index fb34b0966d80c819ba1df9edbc9203d438f66f22..0b3d9a8205d5f0ddb122e2cf048069006e760fa8 100644 (file)
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -1219,8 +1219,6 @@ static int vmx_set_cr0(unsigned long value)
 
     if ( (value & X86_CR0_PE) && (value & X86_CR0_PG) && !paging_enabled )
     {
-        unsigned long cr4;
-
         /*
          * Trying to enable guest paging.
          * The guest CR3 must be pointing to the guest physical.
@@ -1271,16 +1269,6 @@ static int vmx_set_cr0(unsigned long value)
 #endif
         }
 
-        /* update CR4's PAE if needed */
-        __vmread(GUEST_CR4, &cr4);
-        if ( (!(cr4 & X86_CR4_PAE)) &&
-             test_bit(VMX_CPU_STATE_PAE_ENABLED,
-                      &v->arch.hvm_vmx.cpu_state) )
-        {
-            HVM_DBG_LOG(DBG_LEVEL_1, "enable PAE in cr4\n");
-            __vmwrite(GUEST_CR4, cr4 | X86_CR4_PAE);
-        }
-
         /*
          * Now arch.guest_table points to machine physical.
          */